1. Introduction
Wearable biopotential monitors demand amplifiers that resolve microvolt-level signals such as EEG in the presence of flicker noise and DC electrode offset, all while operating from coin-cell power budgets, motivating chopper-stabilised low-noise analog front-end design.
2. Methodology
A two-stage folded-cascode operational transconductance amplifier was designed in a 180nm CMOS process with a chopper modulator placed at the input stage operating at 4kHz to shift flicker noise out of the signal band, followed by a demodulator and low-pass filter at the output. The design was validated through Cadence Spectre post-layout simulation across process, voltage and temperature corners.
3. Results
Post-layout simulation showed an input-referred noise of 0.82 microvolts RMS over a 0.5 to 100Hz bandwidth, open-loop gain of 86dB, phase margin of 61 degrees, and total power consumption of 38 microwatts from a 1.8V supply, with a common-mode rejection ratio exceeding 78dB across process corners.
4. Conclusion
The chopper-stabilised design achieves noise and power performance suitable for battery-powered ECG and EEG acquisition channels. Future work includes silicon fabrication and bench characterisation against the simulated results.
References
[1] Enz C. C. and Temes G. C., Circuit techniques for reducing offset in op-amps, Proceedings of the IEEE, 1996. [2] Harrison R. R. and Charles C., A low-power low-noise CMOS amplifier for neural recording, IEEE JSSC, 2003. [3] Denison T. et al., A 2 microwatt 100nV/rtHz chopper-stabilized instrumentation amplifier, IEEE JSSC, 2007.